Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
Conventional in-process monitoring techniques employ an “inspection and review” procedure wherein the surface of the wafer is initially scanned by a high-speed, relatively low-resolution inspection tool; for example, an opto-electric converter such as a CCD (charge-coupled device) or a laser. Statistical methods are then employed to produce a defect map showing suspected locations on the wafer having a high probability of a defect. If the number and/or density of the potential defects reaches a predetermined level, an alarm is sounded, indicating that a more detailed look at the potential defect sites is warranted. This technique is known as “total density monitoring” of defects and produces a statistic called the “total defect density”.
When the defect density reaches a predetermined level, a review of the affected wafers is warranted. The review process is carried out by changing the optics of the inspection apparatus to a higher resolution, or using a different apparatus altogether. To perform the review, the defect map is fed to the review apparatus and then redetection and review of each suspected site is performed according to the defect map.
In the technique called redetection, the potential defect sites are each compared to a reference site, such as a comparable location on an adjacent, non-defective die on the same wafer, to positively determine the presence of a defect. A more detailed review procedure is thereafter carried out on the individual defect sites, such as scanning with a CCD to produce a relatively high-resolution image, which is then analyzed using pattern recognition techniques to determine the nature of the defect (e.g., a defective pattern, a particle, or a scratch).
Thus, detailed review procedures which classify defects and point to specific corrective action to prevent future defects are typically carried out only after a large number of such defects are likely to have occurred. As a result, such defects remain largely undetected until a considerable number of wafers have been fabricated and have begun to exhibit problems caused by the defects. This late discovery of defects can result in a low manufacturing yield and reduced production throughput.
Furthermore, because the defects are not classified until an alarm is raised, and the alarm indicates only that a certain number of defects has probably occurred, alarms may also be generated when only an acceptably small amount of defects of a serious type have occurred; i.e., there is no way to determine before the alarm is raised whether the potential defects are likely to warrant corrective action.
Moreover, optical devices such as CCDs are limited in their ability to analyze and accurately identify defect types. Firstly, the resolution of their images is limited by the pixel size. Secondly, since they produce only two-dimensional images, they cannot gather a large amount of information regarding the topography of a defect, or whether it lies on the surface or below the surface of the wafer. Thirdly, brightness due to reflection of light from certain types of defects, such as scratches, overwhelms the CCD and may produce false defect counts and false alarms. Thus, the review is generally done manually, with an operator reviewing each suspected site of interest.
Since it has recently been recognized that monitoring classified defect density is preferable to monitoring total defect density, various methods for classification of defects have been introduced. However, the efficiency of these methods is reduced because there is no agreed-upon set of defect classes. Specifically, different semiconductor fabricators consider different defects to be important and, therefore, use different sets of defect classes. Consequently, prior art classification methods are tailored to specific users.
Another problem with prior art defect classification systems is that, because they are tailored to user-specific classes, they require many examples of defect images to be obtained for each defect class prior to becoming operational. Consequently, prior art systems cannot be used during start-up and ramp-up of a production line.
There exists a need to quickly and meaningfully review semiconductor wafers and automatically classify the defects in order to identify processes causing defects, thereby enabling early corrective action to be taken. This need is becoming more critical as the density of surface features, die sizes, and number of layers in devices increase, requiring the number of defects to be drastically reduced to attain an acceptable manufacturing yield.
There also exists a need for a standardized set of classes which correlate to the causes of defects. However, since different process lines may be sensitive to different defects from one to another, there exists a further need for a defect classification system with the flexibility to accommodate the needs of various users.
There exists a further need for an automatic defect classification system which is operable during start-up and ramp-up of a production line and which requires no example defect images to become operable.